1. Field of the Invention
The present disclosure relates to a memory device, and more particularly, to a memory device and method for improving a speed at which data is read from non-volatile memory.
2. Description of the Related Art
Electrically erasable programmable read-only memory (EEPROM) is widely used as a non-volatile data storage device such as a smart card or an integrated circuit card.
FIG. 1 is a block diagram of a conventional memory device 10. Referring to FIG. 1, the memory device 10 includes a memory cell array 20, a control circuit 30, a high-voltage generator 40, a row decoder 60, and a column decoder 70.
The memory cell array 20 includes a plurality of non-volatile memory cells 21-1 through 21-12 connected between word lines WL_A, WL_B, and WL_C and bit lines BL1, BL2, BL3, and BL4. As is well known to those of ordinary skill in the pertinent art, each of the plurality of non-volatile memory cells 21-1 through 21-12 includes a selection transistor 23 and an EEPROM cell 25.
The control circuit 30 controls the operation of the high-voltage generator 40 in response to a clock signal CLK, a read control signal READ, an erase control signal ERASE, and a program control signal PROG, which are received from a memory controller (not shown).
The high-voltage generator 40 is controlled by the control circuit 30 to generate a predetermined high voltage needed to program or erase data to or from each of the non-volatile memory cells 21-1 through 21-12 and a predetermined high voltage needed to read data from each of the non-volatile memory cells 21-1 through 21-12.
The row decoder 60 enables a high voltage generated by the high-voltage generator 40 to one among the word lines WL_A, WL_B, and WL_C in response to an address ADD. The column decoder 70 selects one among the bit lines BL1, BL2, BL3, and BL4 in response to the address ADD.
FIG. 2 is a timing diagram of a read operation of the memory device 10 illustrated in FIG. 1. Referring to FIGS. 1 and 2, in a data read operation, the word line WL_A or WL_C is selected in response to the address ADD, a voltage of the selected word line WL_A or WL_C increases from a ground voltage (VSS) to a read voltage or a power supply voltage (VDD). Accordingly, data stored in EEPROM cells 21-1 through 21-4 or 21-9 through 21-12 corresponding to the word line WL_A or WL_C are transmitted to the corresponding bit lines BL1 through BL4, respectively.
Since the plurality of EEPROM cells 21-1 through 21-4 or 21-9 through 21-12 are connected to the selected word line WL_A or WL_C and parasitic capacitance is present in the selected word line WL_A or WL_C, it takes a long time T1 to increase the voltage from the ground voltage VSS to the power supply voltage VDD. As a result, it takes the long time T1 to read data from the EEPROM cells 21-1 through 21-4 or 21-9 through 21-12 of the selected word line WL_A or WL_C.